Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partnersworldwideand we are looking for passionateengineers to help achieve that mission.

As Microsoft's cloud business continues togrowthe ability to deploy new offerings and hardware infrastructure on time, inhigh volume with high quality and lowest cost is of paramount importance. To achieve this goal, theAI Silicon Engineering (AISiE)team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,scaleand sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions,insightand industry knowledge to envision and implement future technical solutions that will manage andoptimizethe Cloud infrastructure.

We are looking for aPrincipal Logic Design Engineerto join the team.

• Establish yourself as an integral member of a digital logic design team for the development of AI components withfocuson micro-architectural based functions and features.

• Be responsible forthe logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP.

• Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.

• Interface with physical design (PD), design for test (DFT), and other teams tooptimizetradeoffs within the design.

• Provide technical leadership through mentorship and strong teamwork.

Required qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR equivalent experience.

Other Requirements:

Abilityto meet Microsoft, customer and/or government security screening requirementsarerequiredfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will berequiredto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status(e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred qualifications:

• 8+yearsexpertisein digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.
• 7+ years of experience in synthesis, timing constraints, power / performance / area (PPA)trade-offsand post-silicon debug
• 10+ years of experience in one or more of the following - floating point arithmetic anddatapathdesign, DMA design, subsystem designs/integration, or custom logic design
• 5+ years of experience leading logic design teams
• Multiple successfulASIC tape outs in deep sub-micron technologies
• Experience with scriptinglanguagessuch as Python or Perl
• Experience debugging designs as well as simulation environment
• Knowledge of verification principles, testbenches, UVM, and coverage
• Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs
• Working knowledge of writing assertions,coverageand formal verification